
module DirectDigitalSynthesizer
    #(
        parameter DEPTH=32
    )
    (
        input wire [DEPTH-1:0] i_freq_ctrl,
        input wire [DEPTH-1:0] i_phas_ctrl,
        input wire i_clk,
        input wire i_rst,
        output wire [DEPTH-1:0] o_WaveAddr
    );

    reg [DEPTH-1:0] freq_ctrl;
    reg [DEPTH-1:0] phas_ctrl;
    reg [DEPTH-1:0] Acc_out;

    always@(posedge i_clk or posedge i_rst) begin
        if(i_rst) begin
            freq_ctrl	<=	'b0;
		    phas_ctrl	<=	'b0;
		    Acc_out		<=	'b0;
        end
        else begin
            freq_ctrl	<=	i_freq_ctrl;
		    phas_ctrl	<=	i_phas_ctrl;
		    Acc_out		<=	Acc_out+freq_ctrl;
        end
    end
    assign o_WaveAddr	=	Acc_out	+	phas_ctrl;

endmodule
